WebSVN – Tronxy-X3A-Marlin – Blame – /Marlin/fastio_1280.h

Rev	Author	Line No.	Line
1	ron	1	`/**`
		2	`* Marlin 3D Printer Firmware`
		3	`* Copyright (C) 2016 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]`
		4	`*`
		5	`* Based on Sprinter and grbl.`
		6	`* Copyright (C) 2011 Camiel Gubbels / Erik van der Zalm`
		7	`*`
		8	`* This program is free software: you can redistribute it and/or modify`
		9	`* it under the terms of the GNU General Public License as published by`
		10	`* the Free Software Foundation, either version 3 of the License, or`
		11	`* (at your option) any later version.`
		12	`*`
		13	`* This program is distributed in the hope that it will be useful,`
		14	`* but WITHOUT ANY WARRANTY; without even the implied warranty of`
		15	`* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
		16	`* GNU General Public License for more details.`
		17	`*`
		18	`* You should have received a copy of the GNU General Public License`
		19	`* along with this program. If not, see <http://www.gnu.org/licenses/>.`
		20	`*`
		21	`*/`
		22
		23	`/**`
		24	`* Pin mapping for the 1280 and 2560`
		25	`*`
		26	`* Hardware Pin : 02 03 06 07 01 05 15 16 17 18 23 24 25 26 64 63 13 12 46 45 44 43 78 77 76 75 74 73 72 71 60 59 58 57 56 55 54 53 50 70 52 51 42 41 40 39 38 37 36 35 22 21 20 19 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 04 08 09 10 11 14 27 28 29 30 31 32 33 34 47 48 49 61 62 65 66 67 68 69 79 80 81 98 99 100`
		27	`* Port : E0 E1 E4 E5 G5 E3 H3 H4 H5 H6 B4 B5 B6 B7 J1 J0 H1 H0 D3 D2 D1 D0 A0 A1 A2 A3 A4 A5 A6 A7 C7 C6 C5 C4 C3 C2 C1 C0 D7 G2 G1 G0 L7 L6 L5 L4 L3 L2 L1 L0 B3 B2 B1 B0 F0 F1 F2 F3 F4 F5 F6 F7 K0 K1 K2 K3 K4 K5 K6 K7 E2 E6 E7 xx xx H2 H7 G3 G4 xx xx xx xx xx D4 D5 D6 xx xx J2 J3 J4 J5 J6 J7 xx xx xx xx xx`
		28	`* Logical Pin : 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx`
		29	`*/`
		30
		31	`#ifndef _FASTIO_1280`
		32	`#define _FASTIO_1280`
		33
		34	`#include "fastio.h"`
		35
		36	`// change for your board`
		37	`#define DEBUG_LED DIO21`
		38
		39	`// UART`
		40	`#define RXD DIO0`
		41	`#define TXD DIO1`
		42
		43	`// SPI`
		44	`#define SCK DIO52`
		45	`#define MISO DIO50`
		46	`#define MOSI DIO51`
		47	`#define SS DIO53`
		48
		49	`// TWI (I2C)`
		50	`#define SCL DIO21`
		51	`#define SDA DIO20`
		52
		53	`// Timers and PWM`
		54	`#define OC0A DIO13`
		55	`#define OC0B DIO4`
		56	`#define OC1A DIO11`
		57	`#define OC1B DIO12`
		58	`#define OC2A DIO10`
		59	`#define OC2B DIO9`
		60	`#define OC3A DIO5`
		61	`#define OC3B DIO2`
		62	`#define OC3C DIO3`
		63	`#define OC4A DIO6`
		64	`#define OC4B DIO7`
		65	`#define OC4C DIO8`
		66	`#define OC5A DIO46`
		67	`#define OC5B DIO45`
		68	`#define OC5C DIO44`
		69
		70	`// Digital I/O`
		71
		72	`#define DIO0_PIN PINE0`
		73	`#define DIO0_RPORT PINE`
		74	`#define DIO0_WPORT PORTE`
		75	`#define DIO0_DDR DDRE`
		76	`#define DIO0_PWM NULL`
		77
		78	`#define DIO1_PIN PINE1`
		79	`#define DIO1_RPORT PINE`
		80	`#define DIO1_WPORT PORTE`
		81	`#define DIO1_DDR DDRE`
		82	`#define DIO1_PWM NULL`
		83
		84	`#define DIO2_PIN PINE4`
		85	`#define DIO2_RPORT PINE`
		86	`#define DIO2_WPORT PORTE`
		87	`#define DIO2_DDR DDRE`
		88	`#define DIO2_PWM &OCR3BL`
		89
		90	`#define DIO3_PIN PINE5`
		91	`#define DIO3_RPORT PINE`
		92	`#define DIO3_WPORT PORTE`
		93	`#define DIO3_DDR DDRE`
		94	`#define DIO3_PWM &OCR3CL`
		95
		96	`#define DIO4_PIN PING5`
		97	`#define DIO4_RPORT PING`
		98	`#define DIO4_WPORT PORTG`
		99	`#define DIO4_DDR DDRG`
		100	`#define DIO4_PWM &OCR0B`
		101
		102	`#define DIO5_PIN PINE3`
		103	`#define DIO5_RPORT PINE`
		104	`#define DIO5_WPORT PORTE`
		105	`#define DIO5_DDR DDRE`
		106	`#define DIO5_PWM &OCR3AL`
		107
		108	`#define DIO6_PIN PINH3`
		109	`#define DIO6_RPORT PINH`
		110	`#define DIO6_WPORT PORTH`
		111	`#define DIO6_DDR DDRH`
		112	`#define DIO6_PWM &OCR4AL`
		113
		114	`#define DIO7_PIN PINH4`
		115	`#define DIO7_RPORT PINH`
		116	`#define DIO7_WPORT PORTH`
		117	`#define DIO7_DDR DDRH`
		118	`#define DIO7_PWM &OCR4BL`
		119
		120	`#define DIO8_PIN PINH5`
		121	`#define DIO8_RPORT PINH`
		122	`#define DIO8_WPORT PORTH`
		123	`#define DIO8_DDR DDRH`
		124	`#define DIO8_PWM &OCR4CL`
		125
		126	`#define DIO9_PIN PINH6`
		127	`#define DIO9_RPORT PINH`
		128	`#define DIO9_WPORT PORTH`
		129	`#define DIO9_DDR DDRH`
		130	`#define DIO9_PWM &OCR2B`
		131
		132	`#define DIO10_PIN PINB4`
		133	`#define DIO10_RPORT PINB`
		134	`#define DIO10_WPORT PORTB`
		135	`#define DIO10_DDR DDRB`
		136	`#define DIO10_PWM &OCR2A`
		137
		138	`#define DIO11_PIN PINB5`
		139	`#define DIO11_RPORT PINB`
		140	`#define DIO11_WPORT PORTB`
		141	`#define DIO11_DDR DDRB`
		142	`#define DIO11_PWM NULL`
		143
		144	`#define DIO12_PIN PINB6`
		145	`#define DIO12_RPORT PINB`
		146	`#define DIO12_WPORT PORTB`
		147	`#define DIO12_DDR DDRB`
		148	`#define DIO12_PWM NULL`
		149
		150	`#define DIO13_PIN PINB7`
		151	`#define DIO13_RPORT PINB`
		152	`#define DIO13_WPORT PORTB`
		153	`#define DIO13_DDR DDRB`
		154	`#define DIO13_PWM &OCR0A`
		155
		156	`#define DIO14_PIN PINJ1`
		157	`#define DIO14_RPORT PINJ`
		158	`#define DIO14_WPORT PORTJ`
		159	`#define DIO14_DDR DDRJ`
		160	`#define DIO14_PWM NULL`
		161
		162	`#define DIO15_PIN PINJ0`
		163	`#define DIO15_RPORT PINJ`
		164	`#define DIO15_WPORT PORTJ`
		165	`#define DIO15_DDR DDRJ`
		166	`#define DIO15_PWM NULL`
		167
		168	`#define DIO16_PIN PINH1`
		169	`#define DIO16_RPORT PINH`
		170	`#define DIO16_WPORT PORTH`
		171	`#define DIO16_DDR DDRH`
		172	`#define DIO16_PWM NULL`
		173
		174	`#define DIO17_PIN PINH0`
		175	`#define DIO17_RPORT PINH`
		176	`#define DIO17_WPORT PORTH`
		177	`#define DIO17_DDR DDRH`
		178	`#define DIO17_PWM NULL`
		179
		180	`#define DIO18_PIN PIND3`
		181	`#define DIO18_RPORT PIND`
		182	`#define DIO18_WPORT PORTD`
		183	`#define DIO18_DDR DDRD`
		184	`#define DIO18_PWM NULL`
		185
		186	`#define DIO19_PIN PIND2`
		187	`#define DIO19_RPORT PIND`
		188	`#define DIO19_WPORT PORTD`
		189	`#define DIO19_DDR DDRD`
		190	`#define DIO19_PWM NULL`
		191
		192	`#define DIO20_PIN PIND1`
		193	`#define DIO20_RPORT PIND`
		194	`#define DIO20_WPORT PORTD`
		195	`#define DIO20_DDR DDRD`
		196	`#define DIO20_PWM NULL`
		197
		198	`#define DIO21_PIN PIND0`
		199	`#define DIO21_RPORT PIND`
		200	`#define DIO21_WPORT PORTD`
		201	`#define DIO21_DDR DDRD`
		202	`#define DIO21_PWM NULL`
		203
		204	`#define DIO22_PIN PINA0`
		205	`#define DIO22_RPORT PINA`
		206	`#define DIO22_WPORT PORTA`
		207	`#define DIO22_DDR DDRA`
		208	`#define DIO22_PWM NULL`
		209
		210	`#define DIO23_PIN PINA1`
		211	`#define DIO23_RPORT PINA`
		212	`#define DIO23_WPORT PORTA`
		213	`#define DIO23_DDR DDRA`
		214	`#define DIO23_PWM NULL`
		215
		216	`#define DIO24_PIN PINA2`
		217	`#define DIO24_RPORT PINA`
		218	`#define DIO24_WPORT PORTA`
		219	`#define DIO24_DDR DDRA`
		220	`#define DIO24_PWM NULL`
		221
		222	`#define DIO25_PIN PINA3`
		223	`#define DIO25_RPORT PINA`
		224	`#define DIO25_WPORT PORTA`
		225	`#define DIO25_DDR DDRA`
		226	`#define DIO25_PWM NULL`
		227
		228	`#define DIO26_PIN PINA4`
		229	`#define DIO26_RPORT PINA`
		230	`#define DIO26_WPORT PORTA`
		231	`#define DIO26_DDR DDRA`
		232	`#define DIO26_PWM NULL`
		233
		234	`#define DIO27_PIN PINA5`
		235	`#define DIO27_RPORT PINA`
		236	`#define DIO27_WPORT PORTA`
		237	`#define DIO27_DDR DDRA`
		238	`#define DIO27_PWM NULL`
		239
		240	`#define DIO28_PIN PINA6`
		241	`#define DIO28_RPORT PINA`
		242	`#define DIO28_WPORT PORTA`
		243	`#define DIO28_DDR DDRA`
		244	`#define DIO28_PWM NULL`
		245
		246	`#define DIO29_PIN PINA7`
		247	`#define DIO29_RPORT PINA`
		248	`#define DIO29_WPORT PORTA`
		249	`#define DIO29_DDR DDRA`
		250	`#define DIO29_PWM NULL`
		251
		252	`#define DIO30_PIN PINC7`
		253	`#define DIO30_RPORT PINC`
		254	`#define DIO30_WPORT PORTC`
		255	`#define DIO30_DDR DDRC`
		256	`#define DIO30_PWM NULL`
		257
		258	`#define DIO31_PIN PINC6`
		259	`#define DIO31_RPORT PINC`
		260	`#define DIO31_WPORT PORTC`
		261	`#define DIO31_DDR DDRC`
		262	`#define DIO31_PWM NULL`
		263
		264	`#define DIO32_PIN PINC5`
		265	`#define DIO32_RPORT PINC`
		266	`#define DIO32_WPORT PORTC`
		267	`#define DIO32_DDR DDRC`
		268	`#define DIO32_PWM NULL`
		269
		270	`#define DIO33_PIN PINC4`
		271	`#define DIO33_RPORT PINC`
		272	`#define DIO33_WPORT PORTC`
		273	`#define DIO33_DDR DDRC`
		274	`#define DIO33_PWM NULL`
		275
		276	`#define DIO34_PIN PINC3`
		277	`#define DIO34_RPORT PINC`
		278	`#define DIO34_WPORT PORTC`
		279	`#define DIO34_DDR DDRC`
		280	`#define DIO34_PWM NULL`
		281
		282	`#define DIO35_PIN PINC2`
		283	`#define DIO35_RPORT PINC`
		284	`#define DIO35_WPORT PORTC`
		285	`#define DIO35_DDR DDRC`
		286	`#define DIO35_PWM NULL`
		287
		288	`#define DIO36_PIN PINC1`
		289	`#define DIO36_RPORT PINC`
		290	`#define DIO36_WPORT PORTC`
		291	`#define DIO36_DDR DDRC`
		292	`#define DIO36_PWM NULL`
		293
		294	`#define DIO37_PIN PINC0`
		295	`#define DIO37_RPORT PINC`
		296	`#define DIO37_WPORT PORTC`
		297	`#define DIO37_DDR DDRC`
		298	`#define DIO37_PWM NULL`
		299
		300	`#define DIO38_PIN PIND7`
		301	`#define DIO38_RPORT PIND`
		302	`#define DIO38_WPORT PORTD`
		303	`#define DIO38_DDR DDRD`
		304	`#define DIO38_PWM NULL`
		305
		306	`#define DIO39_PIN PING2`
		307	`#define DIO39_RPORT PING`
		308	`#define DIO39_WPORT PORTG`
		309	`#define DIO39_DDR DDRG`
		310	`#define DIO39_PWM NULL`
		311
		312	`#define DIO40_PIN PING1`
		313	`#define DIO40_RPORT PING`
		314	`#define DIO40_WPORT PORTG`
		315	`#define DIO40_DDR DDRG`
		316	`#define DIO40_PWM NULL`
		317
		318	`#define DIO41_PIN PING0`
		319	`#define DIO41_RPORT PING`
		320	`#define DIO41_WPORT PORTG`
		321	`#define DIO41_DDR DDRG`
		322	`#define DIO41_PWM NULL`
		323
		324	`#define DIO42_PIN PINL7`
		325	`#define DIO42_RPORT PINL`
		326	`#define DIO42_WPORT PORTL`
		327	`#define DIO42_DDR DDRL`
		328	`#define DIO42_PWM NULL`
		329
		330	`#define DIO43_PIN PINL6`
		331	`#define DIO43_RPORT PINL`
		332	`#define DIO43_WPORT PORTL`
		333	`#define DIO43_DDR DDRL`
		334	`#define DIO43_PWM NULL`
		335
		336	`#define DIO44_PIN PINL5`
		337	`#define DIO44_RPORT PINL`
		338	`#define DIO44_WPORT PORTL`
		339	`#define DIO44_DDR DDRL`
		340	`#define DIO44_PWM &OCR5CL`
		341
		342	`#define DIO45_PIN PINL4`
		343	`#define DIO45_RPORT PINL`
		344	`#define DIO45_WPORT PORTL`
		345	`#define DIO45_DDR DDRL`
		346	`#define DIO45_PWM &OCR5BL`
		347
		348	`#define DIO46_PIN PINL3`
		349	`#define DIO46_RPORT PINL`
		350	`#define DIO46_WPORT PORTL`
		351	`#define DIO46_DDR DDRL`
		352	`#define DIO46_PWM &OCR5AL`
		353
		354	`#define DIO47_PIN PINL2`
		355	`#define DIO47_RPORT PINL`
		356	`#define DIO47_WPORT PORTL`
		357	`#define DIO47_DDR DDRL`
		358	`#define DIO47_PWM NULL`
		359
		360	`#define DIO48_PIN PINL1`
		361	`#define DIO48_RPORT PINL`
		362	`#define DIO48_WPORT PORTL`
		363	`#define DIO48_DDR DDRL`
		364	`#define DIO48_PWM NULL`
		365
		366	`#define DIO49_PIN PINL0`
		367	`#define DIO49_RPORT PINL`
		368	`#define DIO49_WPORT PORTL`
		369	`#define DIO49_DDR DDRL`
		370	`#define DIO49_PWM NULL`
		371
		372	`#define DIO50_PIN PINB3`
		373	`#define DIO50_RPORT PINB`
		374	`#define DIO50_WPORT PORTB`
		375	`#define DIO50_DDR DDRB`
		376	`#define DIO50_PWM NULL`
		377
		378	`#define DIO51_PIN PINB2`
		379	`#define DIO51_RPORT PINB`
		380	`#define DIO51_WPORT PORTB`
		381	`#define DIO51_DDR DDRB`
		382	`#define DIO51_PWM NULL`
		383
		384	`#define DIO52_PIN PINB1`
		385	`#define DIO52_RPORT PINB`
		386	`#define DIO52_WPORT PORTB`
		387	`#define DIO52_DDR DDRB`
		388	`#define DIO52_PWM NULL`
		389
		390	`#define DIO53_PIN PINB0`
		391	`#define DIO53_RPORT PINB`
		392	`#define DIO53_WPORT PORTB`
		393	`#define DIO53_DDR DDRB`
		394	`#define DIO53_PWM NULL`
		395
		396	`#define DIO54_PIN PINF0`
		397	`#define DIO54_RPORT PINF`
		398	`#define DIO54_WPORT PORTF`
		399	`#define DIO54_DDR DDRF`
		400	`#define DIO54_PWM NULL`
		401
		402	`#define DIO55_PIN PINF1`
		403	`#define DIO55_RPORT PINF`
		404	`#define DIO55_WPORT PORTF`
		405	`#define DIO55_DDR DDRF`
		406	`#define DIO55_PWM NULL`
		407
		408	`#define DIO56_PIN PINF2`
		409	`#define DIO56_RPORT PINF`
		410	`#define DIO56_WPORT PORTF`
		411	`#define DIO56_DDR DDRF`
		412	`#define DIO56_PWM NULL`
		413
		414	`#define DIO57_PIN PINF3`
		415	`#define DIO57_RPORT PINF`
		416	`#define DIO57_WPORT PORTF`
		417	`#define DIO57_DDR DDRF`
		418	`#define DIO57_PWM NULL`
		419
		420	`#define DIO58_PIN PINF4`
		421	`#define DIO58_RPORT PINF`
		422	`#define DIO58_WPORT PORTF`
		423	`#define DIO58_DDR DDRF`
		424	`#define DIO58_PWM NULL`
		425
		426	`#define DIO59_PIN PINF5`
		427	`#define DIO59_RPORT PINF`
		428	`#define DIO59_WPORT PORTF`
		429	`#define DIO59_DDR DDRF`
		430	`#define DIO59_PWM NULL`
		431
		432	`#define DIO60_PIN PINF6`
		433	`#define DIO60_RPORT PINF`
		434	`#define DIO60_WPORT PORTF`
		435	`#define DIO60_DDR DDRF`
		436	`#define DIO60_PWM NULL`
		437
		438	`#define DIO61_PIN PINF7`
		439	`#define DIO61_RPORT PINF`
		440	`#define DIO61_WPORT PORTF`
		441	`#define DIO61_DDR DDRF`
		442	`#define DIO61_PWM NULL`
		443
		444	`#define DIO62_PIN PINK0`
		445	`#define DIO62_RPORT PINK`
		446	`#define DIO62_WPORT PORTK`
		447	`#define DIO62_DDR DDRK`
		448	`#define DIO62_PWM NULL`
		449
		450	`#define DIO63_PIN PINK1`
		451	`#define DIO63_RPORT PINK`
		452	`#define DIO63_WPORT PORTK`
		453	`#define DIO63_DDR DDRK`
		454	`#define DIO63_PWM NULL`
		455
		456	`#define DIO64_PIN PINK2`
		457	`#define DIO64_RPORT PINK`
		458	`#define DIO64_WPORT PORTK`
		459	`#define DIO64_DDR DDRK`
		460	`#define DIO64_PWM NULL`
		461
		462	`#define DIO65_PIN PINK3`
		463	`#define DIO65_RPORT PINK`
		464	`#define DIO65_WPORT PORTK`
		465	`#define DIO65_DDR DDRK`
		466	`#define DIO65_PWM NULL`
		467
		468	`#define DIO66_PIN PINK4`
		469	`#define DIO66_RPORT PINK`
		470	`#define DIO66_WPORT PORTK`
		471	`#define DIO66_DDR DDRK`
		472	`#define DIO66_PWM NULL`
		473
		474	`#define DIO67_PIN PINK5`
		475	`#define DIO67_RPORT PINK`
		476	`#define DIO67_WPORT PORTK`
		477	`#define DIO67_DDR DDRK`
		478	`#define DIO67_PWM NULL`
		479
		480	`#define DIO68_PIN PINK6`
		481	`#define DIO68_RPORT PINK`
		482	`#define DIO68_WPORT PORTK`
		483	`#define DIO68_DDR DDRK`
		484	`#define DIO68_PWM NULL`
		485
		486	`#define DIO69_PIN PINK7`
		487	`#define DIO69_RPORT PINK`
		488	`#define DIO69_WPORT PORTK`
		489	`#define DIO69_DDR DDRK`
		490	`#define DIO69_PWM NULL`
		491
		492	`#define DIO70_PIN PING4`
		493	`#define DIO70_RPORT PING`
		494	`#define DIO70_WPORT PORTG`
		495	`#define DIO70_DDR DDRG`
		496	`#define DIO70_PWM NULL`
		497
		498	`#define DIO71_PIN PING3`
		499	`#define DIO71_RPORT PING`
		500	`#define DIO71_WPORT PORTG`
		501	`#define DIO71_DDR DDRG`
		502	`#define DIO71_PWM NULL`
		503
		504	`#define DIO72_PIN PINJ2`
		505	`#define DIO72_RPORT PINJ`
		506	`#define DIO72_WPORT PORTJ`
		507	`#define DIO72_DDR DDRJ`
		508	`#define DIO72_PWM NULL`
		509
		510	`#define DIO73_PIN PINJ3`
		511	`#define DIO73_RPORT PINJ`
		512	`#define DIO73_WPORT PORTJ`
		513	`#define DIO73_DDR DDRJ`
		514	`#define DIO73_PWM NULL`
		515
		516	`#define DIO74_PIN PINJ7`
		517	`#define DIO74_RPORT PINJ`
		518	`#define DIO74_WPORT PORTJ`
		519	`#define DIO74_DDR DDRJ`
		520	`#define DIO74_PWM NULL`
		521
		522	`#define DIO75_PIN PINJ4`
		523	`#define DIO75_RPORT PINJ`
		524	`#define DIO75_WPORT PORTJ`
		525	`#define DIO75_DDR DDRJ`
		526	`#define DIO75_PWM NULL`
		527
		528	`#define DIO76_PIN PINJ5`
		529	`#define DIO76_RPORT PINJ`
		530	`#define DIO76_WPORT PORTJ`
		531	`#define DIO76_DDR DDRJ`
		532	`#define DIO76_PWM NULL`
		533
		534	`#define DIO77_PIN PINJ6`
		535	`#define DIO77_RPORT PINJ`
		536	`#define DIO77_WPORT PORTJ`
		537	`#define DIO77_DDR DDRJ`
		538	`#define DIO77_PWM NULL`
		539
		540	`#define DIO78_PIN PINE2`
		541	`#define DIO78_RPORT PINE`
		542	`#define DIO78_WPORT PORTE`
		543	`#define DIO78_DDR DDRE`
		544	`#define DIO78_PWM NULL`
		545
		546	`#define DIO79_PIN PINE6`
		547	`#define DIO79_RPORT PINE`
		548	`#define DIO79_WPORT PORTE`
		549	`#define DIO79_DDR DDRE`
		550	`#define DIO79_PWM NULL`
		551
		552	`#define DIO80_PIN PINE7`
		553	`#define DIO80_RPORT PINE`
		554	`#define DIO80_WPORT PORTE`
		555	`#define DIO80_DDR DDRE`
		556	`#define DIO80_PWM NULL`
		557
		558	`#define DIO81_PIN PIND4`
		559	`#define DIO81_RPORT PIND`
		560	`#define DIO81_WPORT PORTD`
		561	`#define DIO81_DDR DDRD`
		562	`#define DIO81_PWM NULL`
		563
		564	`#define DIO82_PIN PIND5`
		565	`#define DIO82_RPORT PIND`
		566	`#define DIO82_WPORT PORTD`
		567	`#define DIO82_DDR DDRD`
		568	`#define DIO82_PWM NULL`
		569
		570	`#define DIO83_PIN PIND6`
		571	`#define DIO83_RPORT PIND`
		572	`#define DIO83_WPORT PORTD`
		573	`#define DIO83_DDR DDRD`
		574	`#define DIO83_PWM NULL`
		575
		576	`#define DIO84_PIN PINH2`
		577	`#define DIO84_RPORT PINH`
		578	`#define DIO84_WPORT PORTH`
		579	`#define DIO84_DDR DDRH`
		580	`#define DIO84_PWM NULL`
		581
		582	`#define DIO85_PIN PINH7`
		583	`#define DIO85_RPORT PINH`
		584	`#define DIO85_WPORT PORTH`
		585	`#define DIO85_DDR DDRH`
		586	`#define DIO85_PWM NULL`
		587
		588	`#undef PA0`
		589	`#define PA0_PIN PINA0`
		590	`#define PA0_RPORT PINA`
		591	`#define PA0_WPORT PORTA`
		592	`#define PA0_DDR DDRA`
		593	`#define PA0_PWM NULL`
		594	`#undef PA1`
		595	`#define PA1_PIN PINA1`
		596	`#define PA1_RPORT PINA`
		597	`#define PA1_WPORT PORTA`
		598	`#define PA1_DDR DDRA`
		599	`#define PA1_PWM NULL`
		600	`#undef PA2`
		601	`#define PA2_PIN PINA2`
		602	`#define PA2_RPORT PINA`
		603	`#define PA2_WPORT PORTA`
		604	`#define PA2_DDR DDRA`
		605	`#define PA2_PWM NULL`
		606	`#undef PA3`
		607	`#define PA3_PIN PINA3`
		608	`#define PA3_RPORT PINA`
		609	`#define PA3_WPORT PORTA`
		610	`#define PA3_DDR DDRA`
		611	`#define PA3_PWM NULL`
		612	`#undef PA4`
		613	`#define PA4_PIN PINA4`
		614	`#define PA4_RPORT PINA`
		615	`#define PA4_WPORT PORTA`
		616	`#define PA4_DDR DDRA`
		617	`#define PA4_PWM NULL`
		618	`#undef PA5`
		619	`#define PA5_PIN PINA5`
		620	`#define PA5_RPORT PINA`
		621	`#define PA5_WPORT PORTA`
		622	`#define PA5_DDR DDRA`
		623	`#define PA5_PWM NULL`
		624	`#undef PA6`
		625	`#define PA6_PIN PINA6`
		626	`#define PA6_RPORT PINA`
		627	`#define PA6_WPORT PORTA`
		628	`#define PA6_DDR DDRA`
		629	`#define PA6_PWM NULL`
		630	`#undef PA7`
		631	`#define PA7_PIN PINA7`
		632	`#define PA7_RPORT PINA`
		633	`#define PA7_WPORT PORTA`
		634	`#define PA7_DDR DDRA`
		635	`#define PA7_PWM NULL`
		636
		637	`#undef PB0`
		638	`#define PB0_PIN PINB0`
		639	`#define PB0_RPORT PINB`
		640	`#define PB0_WPORT PORTB`
		641	`#define PB0_DDR DDRB`
		642	`#define PB0_PWM NULL`
		643	`#undef PB1`
		644	`#define PB1_PIN PINB1`
		645	`#define PB1_RPORT PINB`
		646	`#define PB1_WPORT PORTB`
		647	`#define PB1_DDR DDRB`
		648	`#define PB1_PWM NULL`
		649	`#undef PB2`
		650	`#define PB2_PIN PINB2`
		651	`#define PB2_RPORT PINB`
		652	`#define PB2_WPORT PORTB`
		653	`#define PB2_DDR DDRB`
		654	`#define PB2_PWM NULL`
		655	`#undef PB3`
		656	`#define PB3_PIN PINB3`
		657	`#define PB3_RPORT PINB`
		658	`#define PB3_WPORT PORTB`
		659	`#define PB3_DDR DDRB`
		660	`#define PB3_PWM NULL`
		661	`#undef PB4`
		662	`#define PB4_PIN PINB4`
		663	`#define PB4_RPORT PINB`
		664	`#define PB4_WPORT PORTB`
		665	`#define PB4_DDR DDRB`
		666	`#define PB4_PWM &OCR2A`
		667	`#undef PB5`
		668	`#define PB5_PIN PINB5`
		669	`#define PB5_RPORT PINB`
		670	`#define PB5_WPORT PORTB`
		671	`#define PB5_DDR DDRB`
		672	`#define PB5_PWM NULL`
		673	`#undef PB6`
		674	`#define PB6_PIN PINB6`
		675	`#define PB6_RPORT PINB`
		676	`#define PB6_WPORT PORTB`
		677	`#define PB6_DDR DDRB`
		678	`#define PB6_PWM NULL`
		679	`#undef PB7`
		680	`#define PB7_PIN PINB7`
		681	`#define PB7_RPORT PINB`
		682	`#define PB7_WPORT PORTB`
		683	`#define PB7_DDR DDRB`
		684	`#define PB7_PWM &OCR0A`
		685
		686	`#undef PC0`
		687	`#define PC0_PIN PINC0`
		688	`#define PC0_RPORT PINC`
		689	`#define PC0_WPORT PORTC`
		690	`#define PC0_DDR DDRC`
		691	`#define PC0_PWM NULL`
		692	`#undef PC1`
		693	`#define PC1_PIN PINC1`
		694	`#define PC1_RPORT PINC`
		695	`#define PC1_WPORT PORTC`
		696	`#define PC1_DDR DDRC`
		697	`#define PC1_PWM NULL`
		698	`#undef PC2`
		699	`#define PC2_PIN PINC2`
		700	`#define PC2_RPORT PINC`
		701	`#define PC2_WPORT PORTC`
		702	`#define PC2_DDR DDRC`
		703	`#define PC2_PWM NULL`
		704	`#undef PC3`
		705	`#define PC3_PIN PINC3`
		706	`#define PC3_RPORT PINC`
		707	`#define PC3_WPORT PORTC`
		708	`#define PC3_DDR DDRC`
		709	`#define PC3_PWM NULL`
		710	`#undef PC4`
		711	`#define PC4_PIN PINC4`
		712	`#define PC4_RPORT PINC`
		713	`#define PC4_WPORT PORTC`
		714	`#define PC4_DDR DDRC`
		715	`#define PC4_PWM NULL`
		716	`#undef PC5`
		717	`#define PC5_PIN PINC5`
		718	`#define PC5_RPORT PINC`
		719	`#define PC5_WPORT PORTC`
		720	`#define PC5_DDR DDRC`
		721	`#define PC5_PWM NULL`
		722	`#undef PC6`
		723	`#define PC6_PIN PINC6`
		724	`#define PC6_RPORT PINC`
		725	`#define PC6_WPORT PORTC`
		726	`#define PC6_DDR DDRC`
		727	`#define PC6_PWM NULL`
		728	`#undef PC7`
		729	`#define PC7_PIN PINC7`
		730	`#define PC7_RPORT PINC`
		731	`#define PC7_WPORT PORTC`
		732	`#define PC7_DDR DDRC`
		733	`#define PC7_PWM NULL`
		734
		735	`#undef PD0`
		736	`#define PD0_PIN PIND0`
		737	`#define PD0_RPORT PIND`
		738	`#define PD0_WPORT PORTD`
		739	`#define PD0_DDR DDRD`
		740	`#define PD0_PWM NULL`
		741	`#undef PD1`
		742	`#define PD1_PIN PIND1`
		743	`#define PD1_RPORT PIND`
		744	`#define PD1_WPORT PORTD`
		745	`#define PD1_DDR DDRD`
		746	`#define PD1_PWM NULL`
		747	`#undef PD2`
		748	`#define PD2_PIN PIND2`
		749	`#define PD2_RPORT PIND`
		750	`#define PD2_WPORT PORTD`
		751	`#define PD2_DDR DDRD`
		752	`#define PD2_PWM NULL`
		753	`#undef PD3`
		754	`#define PD3_PIN PIND3`
		755	`#define PD3_RPORT PIND`
		756	`#define PD3_WPORT PORTD`
		757	`#define PD3_DDR DDRD`
		758	`#define PD3_PWM NULL`
		759	`#undef PD4`
		760	`#define PD4_PIN PIND4`
		761	`#define PD4_RPORT PIND`
		762	`#define PD4_WPORT PORTD`
		763	`#define PD4_DDR DDRD`
		764	`#define PD4_PWM NULL`
		765	`#undef PD5`
		766	`#define PD5_PIN PIND5`
		767	`#define PD5_RPORT PIND`
		768	`#define PD5_WPORT PORTD`
		769	`#define PD5_DDR DDRD`
		770	`#define PD5_PWM NULL`
		771	`#undef PD6`
		772	`#define PD6_PIN PIND6`
		773	`#define PD6_RPORT PIND`
		774	`#define PD6_WPORT PORTD`
		775	`#define PD6_DDR DDRD`
		776	`#define PD6_PWM NULL`
		777	`#undef PD7`
		778	`#define PD7_PIN PIND7`
		779	`#define PD7_RPORT PIND`
		780	`#define PD7_WPORT PORTD`
		781	`#define PD7_DDR DDRD`
		782	`#define PD7_PWM NULL`
		783
		784	`#undef PE0`
		785	`#define PE0_PIN PINE0`
		786	`#define PE0_RPORT PINE`
		787	`#define PE0_WPORT PORTE`
		788	`#define PE0_DDR DDRE`
		789	`#define PE0_PWM NULL`
		790	`#undef PE1`
		791	`#define PE1_PIN PINE1`
		792	`#define PE1_RPORT PINE`
		793	`#define PE1_WPORT PORTE`
		794	`#define PE1_DDR DDRE`
		795	`#define PE1_PWM NULL`
		796	`#undef PE2`
		797	`#define PE2_PIN PINE2`
		798	`#define PE2_RPORT PINE`
		799	`#define PE2_WPORT PORTE`
		800	`#define PE2_DDR DDRE`
		801	`#define PE2_PWM NULL`
		802	`#undef PE3`
		803	`#define PE3_PIN PINE3`
		804	`#define PE3_RPORT PINE`
		805	`#define PE3_WPORT PORTE`
		806	`#define PE3_DDR DDRE`
		807	`#define PE3_PWM &OCR3AL`
		808	`#undef PE4`
		809	`#define PE4_PIN PINE4`
		810	`#define PE4_RPORT PINE`
		811	`#define PE4_WPORT PORTE`
		812	`#define PE4_DDR DDRE`
		813	`#define PE4_PWM &OCR3BL`
		814	`#undef PE5`
		815	`#define PE5_PIN PINE5`
		816	`#define PE5_RPORT PINE`
		817	`#define PE5_WPORT PORTE`
		818	`#define PE5_DDR DDRE`
		819	`#define PE5_PWM &OCR3CL`
		820	`#undef PE6`
		821	`#define PE6_PIN PINE6`
		822	`#define PE6_RPORT PINE`
		823	`#define PE6_WPORT PORTE`
		824	`#define PE6_DDR DDRE`
		825	`#define PE6_PWM NULL`
		826	`#undef PE7`
		827	`#define PE7_PIN PINE7`
		828	`#define PE7_RPORT PINE`
		829	`#define PE7_WPORT PORTE`
		830	`#define PE7_DDR DDRE`
		831	`#define PE7_PWM NULL`
		832
		833	`#undef PF0`
		834	`#define PF0_PIN PINF0`
		835	`#define PF0_RPORT PINF`
		836	`#define PF0_WPORT PORTF`
		837	`#define PF0_DDR DDRF`
		838	`#define PF0_PWM NULL`
		839	`#undef PF1`
		840	`#define PF1_PIN PINF1`
		841	`#define PF1_RPORT PINF`
		842	`#define PF1_WPORT PORTF`
		843	`#define PF1_DDR DDRF`
		844	`#define PF1_PWM NULL`
		845	`#undef PF2`
		846	`#define PF2_PIN PINF2`
		847	`#define PF2_RPORT PINF`
		848	`#define PF2_WPORT PORTF`
		849	`#define PF2_DDR DDRF`
		850	`#define PF2_PWM NULL`
		851	`#undef PF3`
		852	`#define PF3_PIN PINF3`
		853	`#define PF3_RPORT PINF`
		854	`#define PF3_WPORT PORTF`
		855	`#define PF3_DDR DDRF`
		856	`#define PF3_PWM NULL`
		857	`#undef PF4`
		858	`#define PF4_PIN PINF4`
		859	`#define PF4_RPORT PINF`
		860	`#define PF4_WPORT PORTF`
		861	`#define PF4_DDR DDRF`
		862	`#define PF4_PWM NULL`
		863	`#undef PF5`
		864	`#define PF5_PIN PINF5`
		865	`#define PF5_RPORT PINF`
		866	`#define PF5_WPORT PORTF`
		867	`#define PF5_DDR DDRF`
		868	`#define PF5_PWM NULL`
		869	`#undef PF6`
		870	`#define PF6_PIN PINF6`
		871	`#define PF6_RPORT PINF`
		872	`#define PF6_WPORT PORTF`
		873	`#define PF6_DDR DDRF`
		874	`#define PF6_PWM NULL`
		875	`#undef PF7`
		876	`#define PF7_PIN PINF7`
		877	`#define PF7_RPORT PINF`
		878	`#define PF7_WPORT PORTF`
		879	`#define PF7_DDR DDRF`
		880	`#define PF7_PWM NULL`
		881
		882	`#undef PG0`
		883	`#define PG0_PIN PING0`
		884	`#define PG0_RPORT PING`
		885	`#define PG0_WPORT PORTG`
		886	`#define PG0_DDR DDRG`
		887	`#define PG0_PWM NULL`
		888	`#undef PG1`
		889	`#define PG1_PIN PING1`
		890	`#define PG1_RPORT PING`
		891	`#define PG1_WPORT PORTG`
		892	`#define PG1_DDR DDRG`
		893	`#define PG1_PWM NULL`
		894	`#undef PG2`
		895	`#define PG2_PIN PING2`
		896	`#define PG2_RPORT PING`
		897	`#define PG2_WPORT PORTG`
		898	`#define PG2_DDR DDRG`
		899	`#define PG2_PWM NULL`
		900	`#undef PG3`
		901	`#define PG3_PIN PING3`
		902	`#define PG3_RPORT PING`
		903	`#define PG3_WPORT PORTG`
		904	`#define PG3_DDR DDRG`
		905	`#define PG3_PWM NULL`
		906	`#undef PG4`
		907	`#define PG4_PIN PING4`
		908	`#define PG4_RPORT PING`
		909	`#define PG4_WPORT PORTG`
		910	`#define PG4_DDR DDRG`
		911	`#define PG4_PWM NULL`
		912	`#undef PG5`
		913	`#define PG5_PIN PING5`
		914	`#define PG5_RPORT PING`
		915	`#define PG5_WPORT PORTG`
		916	`#define PG5_DDR DDRG`
		917	`#define PG5_PWM &OCR0B`
		918
		919	`#undef PH0`
		920	`#define PH0_PIN PINH0`
		921	`#define PH0_RPORT PINH`
		922	`#define PH0_WPORT PORTH`
		923	`#define PH0_DDR DDRH`
		924	`#define PH0_PWM NULL`
		925	`#undef PH1`
		926	`#define PH1_PIN PINH1`
		927	`#define PH1_RPORT PINH`
		928	`#define PH1_WPORT PORTH`
		929	`#define PH1_DDR DDRH`
		930	`#define PH1_PWM NULL`
		931	`#undef PH2`
		932	`#define PH2_PIN PINH2`
		933	`#define PH2_RPORT PINH`
		934	`#define PH2_WPORT PORTH`
		935	`#define PH2_DDR DDRH`
		936	`#define PH2_PWM NULL`
		937	`#undef PH3`
		938	`#define PH3_PIN PINH3`
		939	`#define PH3_RPORT PINH`
		940	`#define PH3_WPORT PORTH`
		941	`#define PH3_DDR DDRH`
		942	`#define PH3_PWM &OCR4AL`
		943	`#undef PH4`
		944	`#define PH4_PIN PINH4`
		945	`#define PH4_RPORT PINH`
		946	`#define PH4_WPORT PORTH`
		947	`#define PH4_DDR DDRH`
		948	`#define PH4_PWM &OCR4BL`
		949	`#undef PH5`
		950	`#define PH5_PIN PINH5`
		951	`#define PH5_RPORT PINH`
		952	`#define PH5_WPORT PORTH`
		953	`#define PH5_DDR DDRH`
		954	`#define PH5_PWM &OCR4CL`
		955	`#undef PH6`
		956	`#define PH6_PIN PINH6`
		957	`#define PH6_RPORT PINH`
		958	`#define PH6_WPORT PORTH`
		959	`#define PH6_DDR DDRH`
		960	`#define PH6_PWM &OCR2B`
		961	`#undef PH7`
		962	`#define PH7_PIN PINH7`
		963	`#define PH7_RPORT PINH`
		964	`#define PH7_WPORT PORTH`
		965	`#define PH7_DDR DDRH`
		966	`#define PH7_PWM NULL`
		967
		968	`#undef PJ0`
		969	`#define PJ0_PIN PINJ0`
		970	`#define PJ0_RPORT PINJ`
		971	`#define PJ0_WPORT PORTJ`
		972	`#define PJ0_DDR DDRJ`
		973	`#define PJ0_PWM NULL`
		974	`#undef PJ1`
		975	`#define PJ1_PIN PINJ1`
		976	`#define PJ1_RPORT PINJ`
		977	`#define PJ1_WPORT PORTJ`
		978	`#define PJ1_DDR DDRJ`
		979	`#define PJ1_PWM NULL`
		980	`#undef PJ2`
		981	`#define PJ2_PIN PINJ2`
		982	`#define PJ2_RPORT PINJ`
		983	`#define PJ2_WPORT PORTJ`
		984	`#define PJ2_DDR DDRJ`
		985	`#define PJ2_PWM NULL`
		986	`#undef PJ3`
		987	`#define PJ3_PIN PINJ3`
		988	`#define PJ3_RPORT PINJ`
		989	`#define PJ3_WPORT PORTJ`
		990	`#define PJ3_DDR DDRJ`
		991	`#define PJ3_PWM NULL`
		992	`#undef PJ4`
		993	`#define PJ4_PIN PINJ4`
		994	`#define PJ4_RPORT PINJ`
		995	`#define PJ4_WPORT PORTJ`
		996	`#define PJ4_DDR DDRJ`
		997	`#define PJ4_PWM NULL`
		998	`#undef PJ5`
		999	`#define PJ5_PIN PINJ5`
		1000	`#define PJ5_RPORT PINJ`
		1001	`#define PJ5_WPORT PORTJ`
		1002	`#define PJ5_DDR DDRJ`
		1003	`#define PJ5_PWM NULL`
		1004	`#undef PJ6`
		1005	`#define PJ6_PIN PINJ6`
		1006	`#define PJ6_RPORT PINJ`
		1007	`#define PJ6_WPORT PORTJ`
		1008	`#define PJ6_DDR DDRJ`
		1009	`#define PJ6_PWM NULL`
		1010	`#undef PJ7`
		1011	`#define PJ7_PIN PINJ7`
		1012	`#define PJ7_RPORT PINJ`
		1013	`#define PJ7_WPORT PORTJ`
		1014	`#define PJ7_DDR DDRJ`
		1015	`#define PJ7_PWM NULL`
		1016
		1017	`#undef PK0`
		1018	`#define PK0_PIN PINK0`
		1019	`#define PK0_RPORT PINK`
		1020	`#define PK0_WPORT PORTK`
		1021	`#define PK0_DDR DDRK`
		1022	`#define PK0_PWM NULL`
		1023	`#undef PK1`
		1024	`#define PK1_PIN PINK1`
		1025	`#define PK1_RPORT PINK`
		1026	`#define PK1_WPORT PORTK`
		1027	`#define PK1_DDR DDRK`
		1028	`#define PK1_PWM NULL`
		1029	`#undef PK2`
		1030	`#define PK2_PIN PINK2`
		1031	`#define PK2_RPORT PINK`
		1032	`#define PK2_WPORT PORTK`
		1033	`#define PK2_DDR DDRK`
		1034	`#define PK2_PWM NULL`
		1035	`#undef PK3`
		1036	`#define PK3_PIN PINK3`
		1037	`#define PK3_RPORT PINK`
		1038	`#define PK3_WPORT PORTK`
		1039	`#define PK3_DDR DDRK`
		1040	`#define PK3_PWM NULL`
		1041	`#undef PK4`
		1042	`#define PK4_PIN PINK4`
		1043	`#define PK4_RPORT PINK`
		1044	`#define PK4_WPORT PORTK`
		1045	`#define PK4_DDR DDRK`
		1046	`#define PK4_PWM NULL`
		1047	`#undef PK5`
		1048	`#define PK5_PIN PINK5`
		1049	`#define PK5_RPORT PINK`
		1050	`#define PK5_WPORT PORTK`
		1051	`#define PK5_DDR DDRK`
		1052	`#define PK5_PWM NULL`
		1053	`#undef PK6`
		1054	`#define PK6_PIN PINK6`
		1055	`#define PK6_RPORT PINK`
		1056	`#define PK6_WPORT PORTK`
		1057	`#define PK6_DDR DDRK`
		1058	`#define PK6_PWM NULL`
		1059	`#undef PK7`
		1060	`#define PK7_PIN PINK7`
		1061	`#define PK7_RPORT PINK`
		1062	`#define PK7_WPORT PORTK`
		1063	`#define PK7_DDR DDRK`
		1064	`#define PK7_PWM NULL`
		1065
		1066	`#undef PL0`
		1067	`#define PL0_PIN PINL0`
		1068	`#define PL0_RPORT PINL`
		1069	`#define PL0_WPORT PORTL`
		1070	`#define PL0_DDR DDRL`
		1071	`#define PL0_PWM NULL`
		1072	`#undef PL1`
		1073	`#define PL1_PIN PINL1`
		1074	`#define PL1_RPORT PINL`
		1075	`#define PL1_WPORT PORTL`
		1076	`#define PL1_DDR DDRL`
		1077	`#define PL1_PWM NULL`
		1078	`#undef PL2`
		1079	`#define PL2_PIN PINL2`
		1080	`#define PL2_RPORT PINL`
		1081	`#define PL2_WPORT PORTL`
		1082	`#define PL2_DDR DDRL`
		1083	`#define PL2_PWM NULL`
		1084	`#undef PL3`
		1085	`#define PL3_PIN PINL3`
		1086	`#define PL3_RPORT PINL`
		1087	`#define PL3_WPORT PORTL`
		1088	`#define PL3_DDR DDRL`
		1089	`#define PL3_PWM &OCR5AL`
		1090	`#undef PL4`
		1091	`#define PL4_PIN PINL4`
		1092	`#define PL4_RPORT PINL`
		1093	`#define PL4_WPORT PORTL`
		1094	`#define PL4_DDR DDRL`
		1095	`#define PL4_PWM &OCR5BL`
		1096	`#undef PL5`
		1097	`#define PL5_PIN PINL5`
		1098	`#define PL5_RPORT PINL`
		1099	`#define PL5_WPORT PORTL`
		1100	`#define PL5_DDR DDRL`
		1101	`#define PL5_PWM &OCR5CL`
		1102	`#undef PL6`
		1103	`#define PL6_PIN PINL6`
		1104	`#define PL6_RPORT PINL`
		1105	`#define PL6_WPORT PORTL`
		1106	`#define PL6_DDR DDRL`
		1107	`#define PL6_PWM NULL`
		1108	`#undef PL7`
		1109	`#define PL7_PIN PINL7`
		1110	`#define PL7_RPORT PINL`
		1111	`#define PL7_WPORT PORTL`
		1112	`#define PL7_DDR DDRL`
		1113	`#define PL7_PWM NULL`
		1114
		1115	`#endif // _FASTIO_1280`

Subversion Repositories Tronxy-X3A-Marlin

(root)/Marlin/fastio_1280.h – Rev 1